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期刊


ISSN0913-5685
刊名電子情報通信学会技術研究報告
参考译名电子信息通信学会技术研究报告：硅器件和材料
收藏年代2000～2023



全部

2000 2001 2002 2009 2013 2014
2015 2017 2020 2021 2022 2023

2001, vol.101, no.107 2001, vol.101, no.108 2001, vol.101, no.246 2001, vol.101, no.247 2001, vol.101, no.320 2001, vol.101, no.321
2001, vol.101, no.350 2001, vol.101, no.430 2001, vol.101, no.515 2001, vol.101, no.571 2001, vol.101, no.573 2001, vol.101, no.718
2001, vol.101, no.719

题名作者出版年年卷期
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni SALICIDES. Inaba; K. Okano; S. Matsuda; M. Fujiwara; A. Hokazono; K. Adachi; K. Ohuchi; H. Suto; H. Fukui; T. Shimizu; S. Mori; H. Oguma; A. Murakoshi; T. Itani; T. Iinuma; T. Kudo; H. Shibata; S. Taniguchi; T. Matsushita; S. Magoshi; Y. Watanabe20012001, vol.101, no.573
A 100nm node CMOS technology for practical SOC applicationAtsuki Ono; Katsuhiko Fukasaku; Tomohiro Hirai; Shin Koyama; Mariko Makabe; Tomoko Matsuda; Michiya Takimoto; Yorinobu Kunimune; Nobuyuki Ikezawa; Yasuhisa Yamada; Fumio Koba; Kiyotaka Imai; Norio Nakamura20012001, vol.101, no.573
SoC CMOS technology for both high reliability and high performanceYukio Nishda; Hirokazu Sayama; Kazunobu Ohta; Hidekazu Oda; Miki Katayama20012001, vol.101, no.573
A 50-nm CMOS technology for high-speed, low-power, and RF applications in 100-nm node SoC platformK. Ohnishi; R. Tsuchiya; T. Yamauchi; F. Ootsuka; K. Mitsuda; M. Hase; T. Nakamura; T. Kawahara; T. Onai20012001, vol.101, no.573
70 nm SOI-CMOS of 135 GHzf{sub}(max) with dual offset-implanted source-drain extension structure for RF/analog and logic applicationsT. Matsumoto; S. Maeda; K. Ota; Y. Hirano; K. Eikyu; H. Sayama; T. Iwamatsu; K. Yamamoto; T. Katoh; Y. Yamaguchi; T. Ipposhi; H. Oda; S. Maegawa; Y. Inoue; M. Inuishi20012001, vol.101, no.573
Proposal of an artificial fingerprint device (AFD) module using poly-Si thin film transistors with logic LSI compatible process for built-in securityS. Maeda; H. Kuriyama; T. Ipposhi; S. Maegawa; M. Inuishi20012001, vol.101, no.573
Novel ultra high density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cellKazushi Kinoshita; Tetsuo Endoh; Takuji Tanigami; Yoshihisa Wada; Kota Sato; Kazuya Yamada; Takashi Yokoyama; Noboru Takeuchi; Kenichi Tanaka; Nobuyoshi Awaya; Keizou Sakiyama; Fujio Masuoka20012001, vol.101, no.573
Analytical model of the trap-density-dependent programming characteristics of MONOS memories and its application to a MONOS memoryKazumasa Nomoto; Ichiro Fujiwara; Hiroshi Aozasa; Toshio Terano; Toshio Kobayashi20012001, vol.101, no.573
A 185 GHz f{sub}(max) SOI DTMOS with a new metallic overlay-gate for low-power RF applications the format of technical reportTatsuya Hirose; Youich Momiyama; Masato Kosugi; Hideki Kano; Yuu Watanabe; Toshihiro Sugii20012001, vol.101, no.573
FD/DG-SOI MOSFET - a viable approach to overcoming the device scaling limitDigh Hisamoto20012001, vol.101, no.573
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