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会议文集


文集名MBMV 2021 - Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
会议名24. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen" (MBMV 2021)
中译名《第二十四届电路和系统建模和验证的方法与描述语言讨论会》
机构Verband der Elektrotechnik Elektronik Informationstechnik e.V. (VDE)
会议日期18-19 March 2021
会议地点Online
出版年2021
馆藏号hyw07622


题名作者出版年
Starkung deterministischer Strategien fur POMDPsLeonore Winterer; Ralf Wimmer; Nils Jansen; Bernd Becker2021
Der Open-Source-DRAM-Simulator DRAMSys4.0Lukas Steiner; Matthias Jung; Norbert Wehn2021
QEMU zur Simulation von Worst-Case-AusfuhrungszeitenPeer Adelt; Bastian Koppelmann; Wolfgang Mueller; Christoph Scheytt2021
Approximate Computing Extensions for the Clash HDL CompilerOliver Keszocze; Michael Kiessling2021
Benchmarking SMT Solvers on Automotive CodeLukas Mentel; Karsten Scheibler; Felix Winterer; Bernd Becker; Tino Teige2021
VP-based DIFT for Embedded Binaries: A RISC-V Case StudyPascal Pieper; Vladimir Herdt; Daniel Grosse; Rolf Drechsler2021
Ontology Design for Microelectronics with Roadmapping (Work-in-progress)Frank Wawrzik; Christoph Grimm2021
A Matter of Overhead - Response Time Analysis of Hard Real-Time Systems in Theory and PracticeMax Brand; Albrecht Mayer; Frank Slomka2021
Exploration of DDR5 with the Open-Source Simulator DRAMSysLukas Steiner; Matthias Jung; Norbert Wehn2021
Comprehensive modeling and evaluation of Network-on-Chip performabilityJie Hou; Martin Radetzki2021
Decision Tree-based Throughput Estimation to Accelerate Design Space Exploration for Multi-Core ApplicationsMartin Letras; Joachim Falk; Jurgen Teich2021
ICP and IC3 with Stronger GeneralizationFelix Winterer; Tobias Seufert; Karsten Scheibler; Tino Teige; Christoph Scholl; Bernd Becker2021
Viability of Decision Trees for Learning Models of SystemsSwantje Plambeck; Lutz Schammer; Goerschwin Fey2021
Constrained Random Verification for RISC-V: Overview, Evaluation and DiscussionSallar Ahmadi-Pour; Vladimir Herdt; Rolf Drechsler2021
Register and Instruction Coverage Analysis for Different RISC-V ISA ModulesPeer Adelt; Bastian Koppelmann; Wolfgang Mueller; Christoph Scheytt2021
APPEL - AGILA ProPErty and Dependency Description LanguageChristoph Grimm; Frank Wawrzik; Alexander Louis-Ferdinand Jung; Konstantin Lubeck; Sebastian Post; Johannes Koch; Oliver Bringmann2021
Extending Verilator to Enable Fault SimulationEndri Kaja; Nicolas Ojeda Leon; Michael Werner; Bogdan Andrei-Tabacaru; Keerthikumara Devarajegowda; Wolfgang Ecker2021
On Self-Verifying DSL Generation for Embedded Systems AutomationZhao Han; Shahzaib Qazi; Michael Werner; Keerthikumara Devarajegowda; Wolfgang Ecker2021
Operation-Level SynthesisLucas Deutschmann; Johannes Schauss; Tobias Ludwig; Dominik Stoffel; Wolfgang Kunz2021
GenMul: Generating Architecturally Complex Multipliers to Challenge Formal Verification ToolAlireza Mahzoon; Daniel Grosse; Rolf Drechsler2021
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